1. Field of the Invention
The present invention relates to semiconductor memory devices using nonvolatile elements such as fuses subjected to laser beam cutting and electric breakdown.
The present application claims priority on Japanese Patent Application No. 2008-127706, the content of which is incorporated herein by reference.
2. Description of Related Art
Conventionally, semiconductor memory devices after manufacturing have been adjusted in terms of timing and internal voltages by use of fuses subjected to laser beam cutting and electric breakdown; however, they suffer from problems in that fuses once broken down are restored, or fuses not subjected to breakdown are accidentally broken down.
For this reason, semiconductor memory devices using fuses subjected to low-reliable electric breakdown are each inspected using two fuses for storing one-bit information, in which inspection is completed upon detection of breakdown of one fuse or upon detection of breakdown of both fuses, thus securing a high reliability.
Various technologies have been developed and disclosed in various documents such as Patent Documents 1 and 2 with respect to methods of determinations (or judgments) of breakdowns of fuses used in semiconductor memory devices.                Patent Document 1: Japanese Unexamined Patent Application Publication No. 2007-80302        Patent Document 2: Japanese Unexamined Patent Application Publication No. 2006-108394        
Patent Document 1 teaches a semiconductor integrated circuit employing a fuse breakdown determination (judgment) method in which two fuses are connected together via a MOS switch so as to operate as an OR circuit, which can perform an OR operation by use of a relatively small area of circuitry. In this method, however, when a failure occurs such that one fuse is short-circuited to a wrong potential which should not be normally connected thereto, the OR circuit cannot operate properly.
Patent Document 2 teaches a semiconductor device using a fuse circuit in which two latch circuits are arranged to store breakdown states of two fuses respectively and are followed by a logic circuit serving as an OR circuit or an AND circuit, thus securing a high reliability in determination of breakdown of fuses.
FIG. 9 shows an example of a semiconductor memory device which is designed based on Patent Document 2, wherein two fuses 101 and 102 are coupled to a fuse breakdown determination judgment) circuit 105 via a selector 104. The fuse breakdown determination circuit 105 determines the breakdown of the fuse 101 or 102 selected by the selector 104, thus outputting a high-level signal. The fuse breakdown determination circuit 105 is followed by latch circuits 106 and 107, AND circuits 108 and 109, and an OR circuit 110. When the fuse breakdown determination circuit 105 determines that one of the fuses 101 and 102 is placed in a breakdown state, the OR circuit 110 outputs a high-level signal, thus completing fuse breakdown determination.
The present inventor has recognized that the semiconductor memory device of FIG. 9 suffers from complexity in which the two fuses 101 and 102 are followed by the two latch circuits 106 and 107. FIG. 10 shows the detailed constitution of the latch circuit 106 (or 107), which needs an OR circuit or an AND circuit in addition to the OR circuit 110. This increases the overall area of circuitry of the semiconductor memory device.